The present invention relates generally to a method of designing an integrated circuit and an apparatus for designing an integrated circuit, and more particularly to a hierarchical parallel processing method of LSI design layout data and an array restructuring method thereof, a CAD (Computer Assisted Design) tool for executing the same methods, and a recording medium recorded with a computer program for executing the same methods.
A layout of a large scale integrated (LSI) circuit has been hierarchically designed over the recent years, and therefore a method and an apparatus for processing design layout data at a high speed have involved the use of a method of processing the design layout data as its hierarchical structure is retained as it is, and a CAD tool. In this case, each of design cells structuring the hierarchical structure is treated in an as-is form of being the design cell.
On one hand, the CAD tool for processing in parallel the design layout data by use of a computer incorporating a plurality of tightly-coupled CPUs or a plurality of computers connected to a network, is used as a technology separate from the hierarchical data processing method.
All of these contrivances aim at speeding up the design layout data processing and reducing an operation-oriented storage file.
On the other hand, for speeding up the processing of the design layout data having a hierarchical structure and reducing the operation-oriented storage file, it is an importance point how an array cell expressed by repetitive pattern data is efficiently treated. The array cell normally involves the use of a secondary array with a large number of repetitions for a general-purpose memory product, and is also used for a memory device such as a RAM and a ROM of a microcomputer. In the case of hierarchically treating the LSI design layout data, when pattern data, cell data or other array data are so laid out as to be overlapped with an array cell data region, it is a data processing method which has hitherto been carried out that the array cell data is developed or converted into unit layout cell data and thus processed.
FIG. 18 is an explanatory diagram showing one example of a layout of an LSI having a hierarchical structure. FIG. 19 is a block diagram showing the hierarchical structure of the LSI shown in FIG. 18.
In the layout of he LSI shown in FIG. 18, as illustrated in the block diagram in FIG. 19, two pieces of cells A, one single cell B and six pieces of cells E are laid out on a Cell ROOT constituting one chip. Further, three pieces of cells C and two pieces of cells D are hierarchically laid out on the cell B. Herein, it is assumed that a size of the Cell ROOT be on the order of 10000 μm×10000 μm, a size of the cell A be on the order of 2000 μm×8000 μm, a size of the cell B be on the order of 3000 μm×3000 μm, a size of the cell C be on the order of 700 μm×700 μm, a size of the cell D be on the order of 1800 μm×600 μm, and a size of the cell E be on the order of 500 μm×1000 μm.
When treating the data while retaining the hierarchical structure of the LSI design layout, the cell has hitherto been dealt with in the as-is form of being the design cell irrespective of a magnitude (a magnitude of a data size) of the number of patterns contained in the design cell, or regardless of a magnitude of the size thereof. For instance, in the example shown in FIG. 18, there are considerable differences in terms of their sizes between the cell ROOT, the cell A, the cell B, the cell C, the cell D and the cell E, and hence these cells ROOT, A, B, C, D and E are treated in their as-designed forms regardless of a considerable difference in the number of patterns contained in the respective cells, i.e., in the data size therebetween. Therefore, when processing the design layout data in parallel by use of a computer incorporating a plurality of tightly-coupled CPUs or by use of a plurality of computers connected to a network, for example, the cell A and the cell E, which are considerably different in size, are treated as processed units at the same level. In an extreme case, a design cell containing only several pieces of pattern data, and an enormous design cell containing several millions of pieces of pattern data are treated as the processed units at the same level.
As a result, there arises the following big problem in the conventional parallel processing of the design layout data.
First, there are treated extremely various types of design cells and, in an extreme case, over several thousands of types of design cells, which leads to an increase in an overhead time for pre-processing/post-processing for starting up a job for executing the parallel processing.
Second, a data quantity of each design cell to be processed in parallel is not uniform and hence each parallel processing time is not uniform. The processing time for the enormous design cells is dominant as an element for determining a time length of the parallel processing time, with the result that an effect of the parallel processing is unable to exhibit.
Further, according to the prior art, when hierarchically treating the LSI design layout data, as in the case of the cells C and D disposed on the cell B, when the pattern data, the cell data or other array data are so disposed as to be overlapped with the array cell data region, the array cell data is developed or converted into unit layout cell data and thus processed. Therefore, it follows that a tremendous number of pieces of pattern data and unit layout cell data are to be treated. This might cause a problem in which the processing time elongates, and a problem in which a large capacity of operation-oriented storage file is needed.